Computer software often runs in parallel on a given computer. For example, a program may have multiple threads executing concurrently or in parallel. At times, these threads may operate on shared data or hardware such as a memory block, a register, an object, a device driver, etc. To avoid data collisions and data corruption, locks are used to allow one thread to lock the shared data. To share an object, for example, a group of threads may each have code that requires acquisition of a lock before accessing the shared object. When a thread has acquired the lock, no other thread can acquire the lock and therefore the thread with the lock has exclusive and deterministic access and control of the shared object.
As processor chips have been built with increasing numbers of cores, the need for efficient locking has increased. Such multicore processors have provided for cache coherency, by which cores can deterministically share data. For example, a chip may implement a cache coherency protocol to implement a coherency model. However, as the number of cores on a single chip increases, cache coherency schemes may not scale well and may become inefficient and complex. Yet, it may not be practical to eliminate all forms of chip-based or hardware-based locking, as parallelism may not be practicable (defeating the purpose of multiple cores) or sharing behavior may become non-deterministic.
It may be desirable to provide locking without the use of complex cache coherency protocols, possibly by using lightweight hardware-based locking mechanisms. Techniques related to hybrid hardware-software locking are discussed below.